FIG. 1 is a cross-sectional view of a representative MOSFET transistor 10 before CMP. The transistor includes a gate region (G) and dopant wells 13 that form a source region (S) and a drain region (D). Electrical connection to the S,G and D regions is typically achieved through vias 16-18 which are made of a conductive material 19, typically tungsten (W) or the like. While the present invention is particularly well suited for treatment of tungsten or like material, it should be realized that the teachings of the present invention are applicable to other conductive materials including but not limited to copper, nickel, silver, gold and other metallic and non-metallic conductive materials.
FIG. 1 represents an in progress stage of transistor fabrication. After deposition of conductive material to fill the via openings, conductive material above the vias is removed to provide appropriate signal isolation. The conductive material is typically removed with a combination of a chemical etchant and mechanical abrasion or polishing.
FIG. 2 illustrates a typical CMP arrangement 21 that includes one or more wafer carriers 20 (three are shown) and a platen 22 provided thereunder for abrasive polishing. A slurry that contains a chemical etchant and abrasive grains is preferably provided on the top surface 23 of the platen. Each carrier 20 holds a wafer 5 and the wafers are brought into contact with the rotating platen (which rotates in the direction of arrow A). The carriers also preferably rotate. The rotating platen machines away the conductive material that has been weakened by the etchant.
While this technique removes conductive material, the amount of conductive material removed from each wafer or from different regions of the same wafer may differ by a significant amount. Stated in other words, prior art polishing processes tend to produce inconsistently or unevenly polished wafers. In prior art assessments, these inconsistencies were often attributed to misalignment of the carriers and the platen and the resultant misdistribution of polishing forces. The below discussed present invention, however, teaches that inconsistently polished wafers are a result of more than polishing force mis-distribution.